clock-tree

基本解释

It reduces switched capacitance by turning off transitions on a clock tree when the triggered registers do not need to change their values.
当暂存器内储存的值不需要改变时，可以藉著关闭时脉讯号的切换来降低切换电容的值。
First, we propose a topology generation method to generate the clock tree topology with minimal output net loading.
首先，我们提出一个时钟树拓朴生成方法来产生拥有最小输出负载的时钟树拓朴。
It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits.
PP-流水线还可以降低流水线电路的时钟树功耗。
Besides, bounded-skew clock tree is proposed to shorten the total wirelength of a clock net, implying lower power dissipation.
除此之外，利用限制时序差异的时钟树可以缩短时脉讯号的线路长度，这也暗示了可以达到更低的功率消耗。
Among clock network designs, the buffered clock tree architecture is the most popular clock network design adopted in modern VLSI designs.
在时钟网路的设计中，目前最普遍采用在现今晶片设计的是缓冲器式时钟树。